Staff Engineer (Logic Pathfinding)
Samsung Semiconductor, San Jose
Phone: +1 (650)-two-seven-two-1873
E-mail: aravindhk947@gmail.com
I’m a semiconductor device engineer working on developing device technology and DTCO boosters for advanced CMOS technology nodes. I apply my expertise in device & circuit engineering and process technology to drive power-performance-area (PPA) improvements through work spanning ring oscillator PPA / cell-level parasitic modeling, semiconductor device modeling, power-delivery circuit design, and process integration. This work has resulted in over 10 U.S. patent filings and includes close collaborations with imec, SRC, and top U.S. research institutions. I earned my Ph.D. from Stanford, where I developed record-low resistance contacts and stable doping techniques for 2D materials like MoS₂, enabling energy-efficient, next-generation transistors.
PhD in Electrical Engineering, Stanford University, 2022 (Defense, Thesis)
Advisor: Prof. Krishna Saraswat
MS in Electrical Engineering, Stanford University, 2018
B.Tech. (Honors) in Electrical Engineering, IIT Bombay, 2016
Minor degrees in Physics and Computer Science