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Staff Engineer (Logic Pathfinding)
Samsung Semiconductor, San Jose
Phone: +1 (650)-two-seven-two-1873
E-mail: aravindhk947@gmail.com
About me
About me
I’m a semiconductor device engineer working on developing technology and DTCO boosters for advanced CMOS technology nodes (1nm and beyond) PPAC. I also work on embedded memory (MRAM, gain-cell) pathfinding for logic applications.
Expertise: device engineering, circuit modeling (parasitic modeling, ring-oscillator PPA), process integration, power-delivery circuits, and nanofabrication.
More than 15 U.S. patent filings, and over 25 peer-reviewed publications with 1000+ citations.
Other responsibilities: Industry Liaison for Semiconductor Research Corporation
Education
Education
PhD in Electrical Engineering, Stanford University, 2022 (Defense, Thesis)
Developed record-low resistance metal contacts and stable doping techniques for 2D materials like MoS₂
Advisor: Prof. Krishna Saraswat
MS in Electrical Engineering, Stanford University, 2018
B.Tech. (Honors) in Electrical Engineering, IIT Bombay, 2016
Minor degrees in Physics and Computer Science
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